1. Field of the Invention
The present invention relates generally to integrated circuits, and in particular, to a circuit and a method for performing write operations with thinly capacitively-coupled thyristor (xe2x80x9cTCCTxe2x80x9d)-based memory cells.
2. Description of Related Art
The rate at which data must be processed is ever increasing in computing-related applications. For example, burgeoning computer graphic applications require faster execution of underlying computational processes to render enhanced three-dimensional images, especially when motion is added. As another example, data network applications demand enhanced computational processes in routing increasing amounts of data (using network elements, such as routers) over decreasing amounts of network bandwidth. The rate at which underlying computational processes are executed depends on the combined functionality of a main processing component, such as a central processing unit (xe2x80x9cCPUxe2x80x9d) and/or a peripheral device (e.g., graphics processor) and, associated memory. Memory includes both data memory, such as cache (e.g., Static Random Access Memory, or xe2x80x9cSRAMxe2x80x9d) and main memory (e.g., Synchronous Dynamic Random Access Memory, or xe2x80x9cSDRAMxe2x80x9d). Data processing rates, however, are generally limited by the manner in which data is exchanged between the processing and memory components, and by the use of conventional memory technology.
Traditionally, the exchange of data between the processing and memory components have been provided by xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d operations. Access between these components can be either for retrieving data or for programming data into memory cells. These operations, however, can hinder computational processing speeds because processor logic is generally faster than memory access time. That is, processing speed is generally limited by the speed at which data can be stored and retrieved from memory. For example, if a processor initiates a traditional read operation during a pending write operation, then it must postpone retrieving data for processing until the write operation has finished.
To improve memory access time, optimized memory access operations have been developed to coordinate memory access so as to optimize overall processing speed. A conventional approach to performing an optimized memory access is the xe2x80x9cread-over-writexe2x80x9d operation. In accordance with read-over-write operations, read operations are scheduled to take precedence over write operations, such that initiating a read will interrupt a pending write operation. Consequently, a memory request for stored data is serviced before data is written into memory, thus permitting continued data processing while the write operation is temporarily bypassed. After the read operation is complete, the bypassed write operation can resume.
To overcome the deficiencies of conventional memory technologies, emerging memory technologies have been developed to improve memory access times and operational speed, as well as to minimize power consumption. One such emerging technology relates to negative differential resistance (xe2x80x9cNDRxe2x80x9d) based devices, and more specifically, to on thinly capacitively coupled thyristor (xe2x80x9cTCCTxe2x80x9d) memory technology. An example of a TCCT cell, alternatively referred to as a T-RAM cell (i.e., Thyristor-RAM), is disclosed in U.S. Pat. No. 6,229,161 issued to Nemati et al., which is incorporated herein by reference in its entirety.
FIG. 1 shows a pair of representative TCCT-based memory cells 10 as disclosed by Nemati et al., and FIG. 2 shows a cross-section through one TCCT-based memory cell 10 along the line 2xe2x80x942. FIG. 3 shows a schematic circuit diagram corresponding to the example of an embodiment illustrated in FIGS. 1 and 2. The TCCT-based memory cell 10 includes an NDR device 12 and a pass transistor 14. A charge-plate or gate-like device 16 is disposed adjacent to, or as shown, surrounding NDR device 12. A P+ region 18 of the NDR device 12 is connected to a metallization layer 20 so that a first voltage V1, such as an array supply voltage (xe2x80x9cVDDAxe2x80x9d) can be applied to the NDR device 12 through the P+ region 18. An N+ region of the NDR device 12 forms a storage node 22 that is connected to a source of the pass transistor 14. Where the pass transistor 14 is a MOSFET, it can be characterized by a channel length, L, and a width, W, where L is the spacing between the source and the drain, and W is the width of the pass transistor 14 in the direction perpendicular to the page of the drawing in FIG. 2. Assuming a constant applied voltage, a current passed by pass transistor 14 will scale proportionally to a ratio of W/L.
As shown in FIGS. 1 and 2, successive TCCT based memory cells 10 are joined by three lines, a bit line 26, a first word line (WL1) 28, and a second-word line (WL2) 30. The bit line 26 (xe2x80x9cBLxe2x80x9d) connects a drain 32 of pass transistor 14 to other TCCT-based memory cells 10. In a similar fashion, pass transistor 14 includes a gate 34 coupled a portion of WL128. Likewise, gate-like device 16 is coupled to a portion of WL230.
In performing a read operation in connection with a TCCT-based memory cell 10, a logic xe2x80x9c1xe2x80x9d will be read out of the cell if the device is in an xe2x80x9conxe2x80x9d state, such that it generates a current representing a logic 1. Similarly, a logic xe2x80x9c0xe2x80x9d will read out of the cell if the device is an xe2x80x9coffxe2x80x9d state, such that it produces essentially no current, and hence no voltage. In performing a write operation, a voltage having a relatively high potential, such as VDD, is applied to the bit line 26 to write a logical xe2x80x9c0xe2x80x9d into a targeted TCCT-based memory cell 10. Conversely, a voltage having a relatively low potential, such as 0 V or ground, is applied to the bit 26 line to write a logical xe2x80x9c1xe2x80x9d into the TCCT-based memory cell. In both cases, WL2 is activated to accomplish writing either a logical xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d into the targeted TCCT-based memory cell 10.
FIG. 4 is a block diagram of circuit 401 depicting arrays of TCCT-based memory cells and reference memory cells arranged in an open-bit architecture. FIG. 4 includes a memory array 400, a reference memory array 414, a WL1/WL2 decoder 402, a RWL decoder 412 and a sense amplification circuit 410. Memory array 400 includes TCCT-based memory cells 404, 406, and reference memory array 414 includes TCCT-based reference memory cells 416, 418.
As shown, memory array 400 is coupled by bit lines BL1, BL2, BL3, etc., to sense amplification circuit 410. Also, reference memory array 414 is coupled by reference bit lines RBL1, RBL2, RBL3, etc., to sense amplification circuit 410. Sense amplification circuit 410 is also connected to complementary input/output lines IO and IOb, which are designed to provide data access between an external source (not shown), such as a CPU, and the memory cells 404, 406.
In array 400, each of memory cells 404, 406 is coupled to a common word line pair (i.e., WL1 and WL2) to form a xe2x80x9crow.xe2x80x9d For example, memory cells 1a, 2a, and 3a associated with word lines WL1a and WL2a form a first row, and memory cells 1b, 2b and 3b associated with word lines WL1b and WL2b form a second row. Similarly, each of reference memory cells 416, 418 in array 414 is coupled to a reference word line (i.e., RWL1) to form at least one row. Each of the rows in array 400, and the row in array 414, are connected to WL1/WL2 decoder 402 and reference RWL decoder 412, respectively.
WL1/WL2 decoder 402 and reference RWL decoder 412 provide for selection of a row during a memory operation. In particular, WL1/WL2 decoder 402 is connected to word lines WL1 and WL2 and decodes at least a portion of a memory address for selecting the appropriate memory cell (or cells, depending on the type of operation, such as block write to a block of memory cells). Similarly, RWL1 decoder 412 is connected to word line RWL1 for selecting the appropriate reference memory cell or cells during, for example, a read operation. Given circuit 401 depicted in FIG. 4, any specific TCCT-based memory cell 404, 406, can be accessed in read, write or other memory operation by applying a specific signal to the appropriate word line or lines.
Although circuit 401 of FIG. 4 can provide for read operations, it is not well-suited to reliably support either write operations or optimized memory access operations, such as read-over-write. Generally, writing to a targeted (i.e., selected for programming) memory cell residing in array 400 has a destructive affect on the nontargeted memory cells (i.e., cells not selected for programming) associated with the same row. The destructive nature of a write operation, unlike the read operation, is due to the activation of word line WL2a that is coupled to an entire row of memory cells, as shown in FIG. 4. In short, given the nature of TCCT-based memory cells, when an activating signal applied to a gate-like device of the thyristor, a unit of data stored previously therein can no longer be considered reliable.
For example, suppose targeted memory cell 406 is associated with a memory address for which data is to be written. During a write operation for circuit 401 of FIG. 4, WL1/WL2 decoder 402 activates targeted memory cell 406 (i.e., cell 1a). Targeted memory cell 406 is activated by applying a relatively high potential (e.g., approximately VDD, or 1.2 V) to word line pair WL1a and WL2a, which is associated with target memory cell 406. Once targeted cell 406 is accessed, write data is driven via input/output lines IO and IOb onto the selected bit line BL2, and correspondingly, into target memory cell 406. When, however, a relatively high potential is applied to gate-like devices 16 of FIG. 2 of each associated memory cell 404, 406 of FIG. 4 (i.e., cells 1a, 2a and 3a), these memory cells are then configured to accept write driven from BL1, BL2 and BL3, respectively. That is, nontargeted memory cells 404 (i.e., cells 1a and 3a) are activated for programming without being written. Hence, the latching state of the TCCT devices in the non-targeted memory cells 1a and 3a most is likely affected, thus making the previously stored data bits from these cells no longer reliable. Consequently, simple open-bit line architectures that have been used with conventional memory technologies are not well-suited to reliably support write operations and read-over-write operations for arrays including TCCT-based memory cells.
Therefore, what is desired is a circuit and a method for providing reliable and non-destructive write operations as well as other optimized memory access operations in connection with TCCT-based memory cells, and arrays thereof, to preserve the integrity of data stored in memory cells not selected for programming. Also, it is desired to provide a circuit and a method that also preserves the relatively low power consumptive nature of TCCT-based arrays during memory access-related operations, such as during write operations.
The present invention provides a circuit and a method for providing non-destructive write operations as well as other optimized memory access operations, such as a read-over write operation, in connection with TCCT-based memory cells. Moreover, the present invention also provides a circuit and a method that preserves the relatively low power consumptive nature of TCCT-based arrays, such as during write operations and other memory access-related operations.
In one embodiment, a memory device for storing one or more data bits is disclosed, where one or more of the data bits is associated with either a first logic state magnitude (to represent a first logic state) or and a second logic state magnitude (to represent a second logic state). The memory device comprises a memory cell configured to store a first data bit, and a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
In another embodiment, the memory cell is a thinly capacitively-coupled thyristor (TCCT) device. In other embodiments, the write access circuit adjusts the write data bit magnitude for only one of either the first logic state or the second logic state associated with the write data bit. For example, the internal logical state magnitude can represent either the first logic state or the second logic state. The intermediate logic state magnitude is between that of the first logic state magnitude and the second logic state magnitude such that there is a reduction in power consumed by the memory device during a memory operation.
In yet another embodiment, a write access circuit is disclosed for programming a memory cell during a write operation. The write access circuit comprises a transfer circuit configured to transfer a data bit during a first portion of the write operation and a driver register circuit configured to store the data bit and to drive a write data bit. The driver-register circuit has an output and an input, with the input coupled to the transfer circuit to receive the data bit. The write access circuit also comprises an adjuster circuit coupled to the output of the driver register circuit. The adjuster circuit, for example, is designed to adjust a characteristic of the write data bit during a second portion of the write operation. In one embodiment the characteristic is the magnitude of the write data bit. In another embodiment, the characteristic is a period of time.